ITT: Cred Forums creates a processor arcitectue

Well, despite the word size being 32 bits, we could just restrict the stack size to 16 bits and use the upper 16 bits of the stack pointer as a general purpose register.
Maybe you could do something hacky with the instruction pointer too.

I assume this is going to be implemented as a virtual machine for ease.

If dubs instruction pointer increments by value in all general registers added together.

There are no general purpose registers lol.

if this ends in a 16 then we have both of these 2 registers be 16GiB

The word size was already decided to be 4 bytes.

Unpipelined

More CORES

Clock speed is 1Hz
Dynamic RAM only
Only subtract for math
Jumps not supported
Stack pointer increments by one, but decrements by two

ARM clone

>2 32bit registers
wew lad

We can work with this. Stack Pointer and IP. Instruction set is like RPN or Forth. Push and pop to/from memory. All operations work on the stack. Instead of flags, we have a cmpjx operator that combines the comparison and jump.

Oh well. We'll just have a stack machine.

Alright boys, we got a 32-bit word size with two registers

next dubs determines address space

2 kb.

Let's make this fun, next post ending in 8 determines ALU operations

2 bytes.

1 MiB

So close

That really is a platform-dependant thing, isn't it?

4GB, max

sqrt
pow
sin
cos
inc
xor

16 bits

I'm not talking about the memory map, I mean the size of the address bus

sp*2

None.

256GiB.

17.5 bits.

4 bits

1024bit

512 bits

2 bits

not + shift only

add
mul
neg

Also everything is a double float.

flat, like dos

3 bits

I'll make the logo

19 bits

sqrt

No one has declared they'll start on the logo? I guess I'll do it then

Okay, you win, how many bits is the bus though?

4

dot product
cross product
simd add
simd sub
simd mul
simd div
sqrt
vector length
vector normalize

Alright Boys, Cred ForumsCPU specs thus far:

-32 word length
-2 registers
-16 bytes of addressable memory

AND
NOT

You guys work something out

NEG

cons car cadr cdr inc dec xor and nor randmask (xor operation with random bits)

Also, if anyone wants to make a virtual machine of this abomination, feel free.

cube root

and flat, DOS-style memory space ya mook

WINRAR

I might attempt it. Not right now though.
We still need to work out the instruction set.

Right, right

Cred ForumsCPU specs:
32 bit word length
2 registers
16 bytes of flat memory
ALU operations: cons car cadr cdr inc dec xor and nor randmask

9 bits

I'm sure professionals design their CPUs like this, too

>16 bytes of flat memory
IT'S OVER, INTEL IS FINISHED

Okay guys, onto the instruction set, dubs determines the amount of opcodes

2

>16 bytes of flat memory

and by this I meant absolutely /no/ memory protection modes, I want to be able to open my master boot sector in a motherfucking bitmap paint program

Why the hell are cons/car/cadr/cdr in the ALU? They should be in the general ISA, they're all indirect pointer-follow instructions.

Cred Forumscpu confirmed for frankenstein alu containing an entire extra mmu

nand
jne

finally, we can crank out binaries 21 questions style or with binary decision trees

>fewer opcodes than alu operations
uh, guys?

This architecture is fucking useless.

Mate, with the amount of address space we have, your operating system is going to consist of two dots on a 16x2 display

Well... shit.

At least try to be a bit more subtle AMD

Imma be kind and add those opcodes onto the ALU operations

so we have 10 opcodes on a 32 bit word length

god help us

We could make it so the first instruction just counts up the IP and the second instruction executes an instruction based on the IP

Needs more pipelines.

>not bitpacking your display drivers

oh yee of little faith

easy.
Push
Exec

Push pushes a word onto the stack
Exec interprets the word on top of the stack as a sub-opcode and executes it.
Dubs decides on sub-opcodes.

Okay guys, next order of business

Next ten posts determine the operations for each opcode.

spaz (randmasks a random address anywhere in memory)

Forgot to mention that Exec also pops the word from the stack.

jump back one instruction

Jump forwards 3 instructions.

cdr
opens cd-rom tray

Ignore this, use 's idea instead

one isa instruction to switch to a different memory segment

(working around the stupid 16 byte flat address map)

thats the ALU ya mook, and its a lisp machine function

fxor

Got to support floating point, right?

Sub-Opcodes thus far:

spaz (randmasks a random address anywhere in memory)

fxor

Keep em' coming, last digit of this post decides how many more sub-opcodes we do

gcc
Invokes the GCC compiler from host

>different memory segment

what about flat addressing don't you understand

wrong

Too bad, we're XORing floats now.

`nnb`

Writes the content of '99 bottles of beer on the wall' to memory at the specified location, or at least, as much of it as will fit. Intended for shitposting on code golf websites

crank (the architecture now includes two lines out of the machine with enough to produce an arc across the terminals, the crank opcode is intended to shock the user or supply negligible pulses to auxillary doodats)

float don't real in 16 bytes of memory

>2 fucking registers
>16 bytes of flat memory
What the fuck did you expect?

trap

Randomizes the opcode to operation mapping for all but this instruction.

maybe not in IEEE754, but abstractly nobody is stopping you having mantissa/exponent taking up as many bits as you want

not?

Conditional negation based on the result of the previous operator.

>stupid 16 byte flat address map

if you've never thrown and pulled opcodes to and fro video memory your basically subhuman

Complete sub-opcodes:
Alright boys, what's next?

rboot
Reboots the cpu

Isn't that the same as adding a reset button?

rboot2

Reboots the CPU twice, although, it's acceptable for ISA implementations to lose track of the number of resets part-way through executing this operation

Yeah, but it will do wonders with trap and spaz

programmers work on emulator in C or Lisp

engineers figure out how to summon this demon into silicon

Pipelines. How many stages and what goes where.

Ruined

Fine, it's in

Alright, dubs determines the number of pipeline stages

4

512

8

0

Not bad.

let's spend 7 of those on translating between mutually incompatible micro-op isas

>and by this I meant absolutely /no/ memory protection modes, I want to be able to open my master boot sector in a motherfucking bitmap paint program
TempleOS

dubs for reserving half the address space for memory mapped devices.

Next dubs determines what each stage does

Retard here. Is there any way to emulate this abomination?

50/50 chance of
Randomizes a random bit of memory or
Actually executing the instruction and placing it in a random place in memory

Sure, with a VM

Dubs decides on video address space.

variable, dynamically allocatable, default standard VGA (what is it like 400 something by 300?)

pull up programs as bitmaps

No video

How you emulate a processor with a VM?

We only have 16 bytes though..

standard DOS-style VGA; we're designing a processor, not a video driver

keep thinking

1 bit

Each pipeline stage complete a whole fetch/exec/writeback cycle

We can use the many remaining sub-opcodes for setting pixels on the screen! Since a word can contain 4 billion codes.

this \/
fantastic idea

best Cred Forums thread in a long while

How are we implementing it, verilog?

C++

Stick and stones on sand.

It seems no-one has enough skillz to know how pipelines work. Maybe we take the latest post in a few minutes?

I want to purchase this processor.

With this shit? Just pipeline the lovecraftian horror of an ALU

All a VM does is emulate a processor